Asymptotic Waveform Evaluation presents an overview of the diverse algorithms and applications of moment matching techniques.
The material is presented systematically and is supported by many examples. Issues such as sensitivity analysis and three-dimensional analysis are also covered.
Asymptotic Waveform Evaluation will be of interest to engineers, students and researchers involved in the development and study of circuit simulation as well as interconnect analysis. Citation: Z. Ruehli, A. Cangellaris, "Progress in the methodologies for the electrical modeling of interconnects and electronic packages ," Proc. IEEE , Vol.
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Circuits Syst. Tan, S.
Rohrer and A. Griffith, E. Department of Electronics. My Wishlist. Zustellung durch.
Zhu, Y. Hoboken, New Jersey, Pillage , L.
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Li, and G. Han, "Application of asymptotic waveform evaluation to eigenmode expansion method for analysis of simultaneous switching noise in printed circuit boards PCBs ," IEEE Trans. Wan, J. There are many methods used for delay calculation for the gate itself.
The choice depends primarily on the speed and accuracy required:. Similarly there are many ways to calculate the delay of a wire.
The delay of a wire will normally be different for each destination. In order of increasing accuracy and decreasing speed , the most common methods are:.
Often, it makes sense to combine the calculation of a gate and all the wire connected to its output. This combination is often called the stage delay.
Asymptotic Waveform Evaluation. And Moment Matching for Interconnect Analysis. Authors: Chiprout, Eli, Nakhla, Michel S. Free Preview. Asymptotic Waveform Evaluation and Moment Matching for Interconnect Analysis Peter Feldmann, Roland W. Freund, Efficient linear circuit analysis by Pade´.
The delay of a wire or gate may also depend on the behaviour of the nearby components. This is one of the main effects that is analyzed during signal integrity checks.
In the context of semi-custom digital design, pre-characterized digital information is often abstracted in the form of the above mentioned 2-D look up table LUT. The idea behind semi-custom design method is to use blocks of pre-built and tested components to build something larger, say, a chip. Although in reality these gates will be composed of transistors, a semi-custom engineer will only be aware of the delay information from input pin to output pin, called a timing arc.